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5GHz Receiver
Table 8. Main Address 9: (A4:A0 = 01001, Main Address 0 D0 = 0)
BIT NAME
TX_GAIN<5:0>
RESERVED
BIT LOCATION
(D0 = LSB)
D9:D4
D3:D0
DESCRIPTION
Tx VGA Gain Control
Tx channel is selected by Main address 9 D3:D0.
000000 = Minimum gain (default)
…
111111 = Minimum gain + 31.5dB
Reserved bits; set to default
Table 9. Main Address 14: (A4:A0 = 01110, Main Address 0 D0 = 0)
BIT NAME
RESERVED
DOUT_SEL
RESERVED
BIT LOCATION
(D0 = LSB)
D9:D2
D1
D0
Reserved bits; set to default
DOUT Pin Output Select
0 = PLL lock detect (default)
1 = SPI readback
Reserved bits; set to default
DESCRIPTION
Table 10. Main Address 15: (A4:A0 = 01111, Main Address 0 D0 = 0)
BIT NAME
VAS_TRIG_EN
RESERVED
SYN_CONFIG_N<6:0>
BIT LOCATION
(D0 = LSB)
D9
D8:D7
D6:D0
DESCRIPTION
Enable VCO Sub-Band Acquisition Triggered by SYN_CONFIG_F<9:0>
(Main Address 17) Programming
0 = Disable for small frequency adjustment (i.e., ~100kHz)
1 = Enable for channel switching (default)
Reserved bits; set to default
Integer Divide Ratio
1000010 = Default
Table 11. Main Address 16: (A4:A0 = 10000, Main Address 0 D0 = 0)
BIT NAME
SYN_CONFIG_F<19:10>
BIT LOCATION
(D0 = LSB)
D9:D0
Fractional Divide Ratio LSBs
0000000000 = Default
DESCRIPTION
24
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